1. Field of the Invention
The present invention relates to a low-power, high-performance inverter circuit, and more particularly to a low-power, high-performance inverter circuit, which achieves high speed operation by preventing a first node, through which a virtual Vss line passes, or a second node, through which a virtual Vdd line passes, from shifting to an excessively high or low voltage level when the first node is shorted to a supply voltage terminal Vdd or when the second node is shorted to a ground terminal, respectively, due to a resistive defect.
2. Description of the Related Art
As power consumption and device reliability in high-density integrated circuits and systems has received increasing attention, power supply voltage has been decreased. Supply voltage is expected to be lower than 1V, particularly in circuits used in low power devices such as portable computers, mobile phones and personal digital assistants (PDA). It is necessary to reduce the threshold voltage of each transistor to secure low supply voltage and high-performance operating characteristics.
However, if semiconductor memory devices use low supply voltage, gate-source voltage |VGS| is reduced, causing lower performance and increasing leakage current of transistors in a standby state. Various circuit techniques have been proposed to overcome these problems. FIG. 1 illustrates a conventional inverter circuit implemented for overcoming the problems.
As shown in FIG. 1, the conventional inverter circuit includes a first inverter 110 for inverting and outputting an input signal IN, and a second inverter 120 for inverting and outputting a signal INi output from the first inverter 110. The first inverter 110 includes a PMOS P11 for pulling up a node A, and an NMOS N11 for pulling down the node A, and the second inverter 120 includes a PMOS P12 for pulling up a node B, and an NMOS N12 for pulling down the node B.
In order to reduce leakage current in standby mode, the conventional inverter circuit further includes a PMOS P13 coupled between the NMOS N11 and a ground terminal Vss, and an NMOS N13 coupled between the PMOS P12 and a supply voltage terminal Vdd. In active mode, −Vdd and 2Vdd are applied to the gates of the PMOS P13 and the NMOS N13 to turn on the PMOS P13 and the NMOS N13, respectively. In standby mode, Vdd and −Vss are applied to the gates of the PMOS P13 and the NMOS N13 to turn off the PMOS P13 and the NMOS N13, respectively, thereby significantly reducing leakage current in standby mode.
In more detail, the PMOS P13 is turned on in active mode by applying a signal S of −Vdd to the gate of the PMOS P13, so that a node C between the NMOS N11 and the PMOS P13 is at Vss level. If the inverter circuit enters standby mode when the input terminal IN of the first inverter 110 is at low level, the voltage of the node C is gradually increased up to a voltage of Vss+ΔV until the NMOS N11 is reverse-biased. Consequently, the NMOS N11 and the PMOS P13 connected to the node C are all reverse-biased, thereby reducing leakage current. Likewise, the NMOS N13 is turned on in active mode by applying a signal SB of 2Vdd to the gate of the NMOS N13, so that a node D between the PMOS P12 and the NMOS N13 is at Vdd level. If the inverter circuit enters standby mode when the input signal INi of the second inverter 120 is at high level, the voltage of the node D is gradually reduced down to a voltage of Vdd−ΔV until the PMOS P12 is reverse-biased. Consequently, the NMOS N13 and the PMOS P12 connected to the node D are all reverse-biased, thereby reducing leakage current.
Despite the advantage of reduced leakage current in standby mode, the conventional inverter circuit has the following problem. If the node C, through which a virtual Vss line passes, is shorted to the supply voltage terminal Vdd, or if the node D, through which a virtual Vdd line passes, is shorted to the ground terminal Vss, due to a resistive defect such as a short caused by dielectric breakdown or bridging between metal lines, the voltage of the node C shifts to a level near “Vdd” much higher than initially intended, or the voltage of the node D shifts to a level near “Vss” much lower than initially intended, which significantly reduces the circuit operation speed. That is, since the voltage of the node C is near Vdd or the voltage of the node D is near Vss due to the short, it takes a long time to shift the node C back to the ground level Vss or the node D back to the supply voltage level Vdd when switching the inverter circuit from standby mode to active mode at a later time, which causes operation delay of the inverter circuit.